Circuits in systems consume dynamic power whenever logic and routing toggle, i.e. change values between 0 and 1. Some toggles are necessary because they represent the intended change in the value of a signal and reflect the final value of the logic for a clock period. Other toggles reflect intermediate values computed by combinatorial logic and are referred to as glitches. Glitches are unwanted because they do not reflect the final value of a combinatorial logic gate for a clock period and consumes power.
For example, consider an observable point in a circuit, P. The inputs of a combinatorial cone of logic driving P is referred to as Support(P). Changes in the value observed at P are caused by changes in Support(P). Glitches may be observed at P whenever multiple transitions occur at P within a single clock period. All transitions except the last are deemed to be glitches. Multiple transitions observed at P may be caused by transitions in the values in Support(P). The multiple transitions may occur in Support(P) and the effects of the multiple transitions arrive at P at different times. Alternatively, a single change in Support(P) may be propagated through multiple paths through the combinatorial logic and those paths may have differing delay.
FIGS. 1a and 1b illustrate an example of glitching. FIG. 1a illustrates an exemplary circuit with input registers RA 101, RB 102, RC 103, an XOR gate Fgate 104, and output register RF 105. In this example, the propagation delay is 1 unit from the output of RA to the input of Fgate, 2 units from the output of RB to the input of Fgate, 5 units from the output of RC to the input of Fgate, 1 unit from each input of Fgate to the output of Fgate, and 1 unit from the output of Fgate to RF. The inputs of the combinatorial cone of logic driving F is Support(F)={RA, RB, RC}. Assuming that the clock skew is negligible and that all three input registers RA, RB, and RC change at the same time, the observed value at F will change three times, once for each change by an input register. The first two changes are glitches, and the last change reflects the final value of the function for that clock cycle. FIG. 1b illustrates an exemplary timing diagram for the circuit shown in FIG. 1a. 
Some types of logic are more susceptible to glitching than others. Logic such as XOR gates, Adders, Multipliers, Multiplexors, crossbars, and barrel shifters tend to be more susceptible to glitching because they tend to generate a change in output in response to any change in their inputs. An AND gate, however, is not susceptible to glitching because it is sensitive to an input bit only if all the other inputs are 1, which is a small fraction of its input space. Glitches are especially harmful when the logic cone is deep. A glitch in an early stage of the logic cone will often propagate through the rest of the logic, and cause a cascade of wasted power.
Thus, what is needed is an efficient and effective method and apparatus for addressing glitching to reduce the dynamic power requirement of a system.